The Mother of All Memory Challenges: Overcoming the Speed-Power Conundrum
As circuit designers, system designers or board designers, we have time and again had to throw down the gauntlet and have been asked to achieve the fastest speeds with the least power dissipation. In the end, we always have had to compromise one thing for the other. Faster speeds come at the price of power, and if we try to be more power-efficient, it might cut corners on the pace of operations.
Static RAMs (SRAM) are no different. On the one hand, until now, the fastest asynchronous SRAM would operate at 100 MHz and drain the battery within hours. On the other hand, SRAMs designed for battery-powered applications, such as handheld devices, would operate at a fifth of the speed of the fast SRAMs (20 MHz) to ensure years of long battery life. Since memory transactions are at the heart of all applications, speed limitations when accessing memory would make the system operate slower.
The good news is that Cypress has solved this speed-power bottleneck on its 65-nm process node. The SRAMs manufactured on this technology are offered with a PowerSnooze™ feature, enabling the SRAMs to operate at fast speeds of 100 MHz, while consuming less than 2 uA / Mbit of sleep current. By invoking this “deep sleep” feature of these SRAMs, you can quickly transition from a high-speed active state to a power-saving sleep state.
The PowerSnooze feature makes Cypress’ SRAMs ideal for industrial applications and IoT systems, where the emphasis is on completing the task quickly and switching to a power-saving state. You can now harness the power of your MCU; the SRAM is no longer a limitation in achieving peak performance. These devices are footprint-compatible with the standard SRAMs, making them easy to design with.
Check out our video on PowerSnooze, shot with a demo kit that has three sets of the classic Pacman character revealing a Cypress logo. Watch it to see who wins the race with the most fuel still left in the tank!