Spansion HyperBus™ Interface enables breakneck read throughput speeds

333 MHz NOR flash memory–Spansion’s new interface promises peak performance for memories and more

NOR flash memory remains the preferred non-volatile technology for discrete memories in embedded systems requiring fast boot and high read throughputs. For applications where the cost-performance balance requires the designer to lean on the side of savings, they have been able to take advantage of NOR flash devices using the lower pin count Serial Peripheral Interface (SPI) to optimize the memory subsystem.  Systems using SPI NOR flash memories have achieved 80 MB/s throughputs using a double data rate (DDR) Quad SPI protocol while retaining compatibility with the original interface specified over 25 years ago.  As system-level read throughput continues to demand ever-increasing speeds, a new look at the embedded memory interface offers a solution.

 

The Spansion HyperBus™ Interface is a low pin-count interface that achieves significantly higher performance than both legacy parallel and SPI interfaces.  The Spansion HyperBus Interface implements a low pin-count bus interface with a simple read/write protocol that is suitable for both memories and peripheral interfaces.   This article outlines the advantages of the Spansion HyperBus Interface as the highest performance NOR flash for embedded applications.  Spansion’s memory portfolio supporting the HyperBus Interface includes the HyperFlash™ family of NOR flash memory products.

 

Pin count and read throughtput comparisons

Two of the more significant criteria used to evaluate NOR flash devices are the sustained read throughput and the number of pins required to implement the bus interface. The legacy parallel interfaces (Async, Page and ADP Burst) all require over 40 pins with an address/data multiplexed version of the parallel bus (ADP) having around 30 pins (see figure 1).  The SPI interface has evolved to include a six-pin Quad-SPI variant (QSPI) that has gained favor when enhanced read throughput is required.  The new Spansion HyperBus Interface at twelve pins offers a significant improvement in efficiency over the parallel interfaces and only requires an additional six pins more than the QSPI.

 

Figure 1: Quad SPI and the HyperBus Interface feature significantly lower pin counts than legacy parallel interfaces like Async, Page and ADP Burst.

Figure 1: Quad SPI and the HyperBus Interface feature significantly lower pin counts than legacy parallel interfaces like Async, Page and ADP Burst.

 

The HyperBus Interface delivers a substantial improvement in read throughput (see figure 2) compared with legacy NOR flash interfaces (see figure 2).  With an 80 MB/s read throughput, QSPI has reached performance levels comparable with the asynchronous and page mode interfaces t.  Burst mode offerings come in around 133 MB/s in environments that expect a mix of wrapped and continuous read transactions.  The HyperFlash memories leveraging the Spansion HyperBus Interface provide a new standard for performance by delivering 333 MB/s using a 12-pin interface.  The 333 MB/s is achieved with the 1.8 V version of the interface; the 3 V version runs at 100 MHz and provides 200 MB/s.

 

Figure 2: Compared to legacy NOR flash interfaces, the HyperBus Interface offers a significant increase in read throughput.

Figure 2: Compared to legacy NOR flash interfaces, the HyperBus Interface offers a significant increase in read throughput.

 

HyperBus Interface Signal Description

The HyperBus Interface is implemented using twelve signals running at either 1.8 V or 3.0 V (see figure 3). The twelve HyperBus Interface signals include:

 

  1. CS# – Chip Select (1)
  2. CK/CK# – Differential Clock (2)
  3. RDS – Read Data Strobe (1)
  4. DQ[7:0] – Command/Address/Data Bus (8)

 

The 12-pin 1.8 V interface uses standard LVCMOS inputs and IOs with a differential clock (CK/CK#).  The 11-pin 3 V interface uses standard 3 V LVCMOS inputs and IOs with a single-ended clock (CK# is not used).  The CS# signal is used by the host controller to enable a single device on the HyperBus Interface.  The enabled device begins a transaction with a high to low transition of CS# and terminates a transaction with a low to high transition of CS#.  The differential CK/CK# clock inputs are output by the host controller to transfer command, target address, and write data on the DQs.  Command/address/write-data information is center aligned with CK/CK# edges in a DDR fashion.  The Read Data Strobe (RDS) signal is an output from the memory that is used during read transactions to identify valid data.  RDS toggles in an edge aligned manner when data is being output by the HyperFlash memory during read transactions.  The DQ signals are used to multiplex command, address and data information in a byte-wide DDR manner.

 

Figure 3: The HyperBus Interface connects host and memory using 12 signals:  chip select (CS#), differential clock (CK, CK#) Read Data Strobe (RDS), and eight channels of command/address/data bus (DQ [7… 0]).

Figure 3: The HyperBus Interface connects host and memory using 12 signals: chip select (CS#), differential clock (CK, CK#) Read Data Strobe (RDS), and eight channels of command/address/data bus (DQ [7… 0]).

HyperBus Interface read and write transactions

All bus transactions can be classified as either Read (see figure 4) or Write (see figure 5). A bus transaction starts with CS# going LOW with CK=LOW and CK#=HIGH. The transaction to be performed is presented to the HyperFlash memory device during the first three clock cycles in a DDR manner using all six clock edges. These first three clocks transfer three words of Command/Address (CA0, CA1, CA2) information to define the transaction characteristics. The following transaction characteristics are defined during the three-clock-cycle Command/Address definition:

  1. Whether the transaction is a Read or Write
  2. Whether the transaction will be to the memory array or to register space
    1. Register space is not supported on HyperFlash NOR devices.  Any read from the register space will return indeterminate data. Writes to the register space are not allowed. Future devices may support the register space.
  3. The target Page address (upper-order address)
  4. The target Word (within Page) address (lowerorder address)
  5. Whether a Read or Write transaction will use continuous or wrapped burst sequencing.
    1. NOR Write transactions are single word (or continuous, in the case of Word Programming).
    2. Future device write transactions may not be limited to a single word and may allow configurations to be either wrapped or continuous.

 

Figure 4: A HyperBus Interface Read transaction begins with three words of Command/Address information (CA0, CA1, CA2) to define the transaction, followed by idle clock cycles (CK, CK#) to satisfy latency demands, followed by a Read step during which data edges are aligned with RDS edges

Figure 4: A HyperBus Interface Read transaction begins with three words of Command/Address information (CA0, CA1, CA2) to define the transaction, followed by idle clock cycles (CK, CK#) to satisfy latency demands, followed by a Read step during which data edges are aligned with RDS edges

 

 

 

 

 

Figure 5: A HyperBus Interface Write transaction begins with CA zero through CA to, followed by data transfer with the data center aligned to the clock transitions.

Figure 5: A HyperBus Interface Write transaction begins with CA zero through CA to, followed by data transfer with the data center aligned to the clock transitions.

 

Once the transaction has been defined during the first three clock cycles, a number of idle clock cycles may be used to satisfy any array latency requirements before data is transferred. Once the target data has been transferred, the host completes the transaction by driving CS# HIGH with CK=LOW and CK#=HIGH. Data is transferred as 16-bit values with the upper eight bits (15-8) transferred on a HIGH going CK (Write data or CA bits) or RDS edge (Read data) and the lower eight bits (7-0) being transferred on the LOW going CK or RDS edge. Data transfers during read or write operations can be ended at any time by bringing CS# HIGH when CK=LOW and CK#=HIGH. Read data is edge aligned with RDS transitions and Write data is center aligned with CK/CK# crossings.

 

The philosophy behind the HyperBus Interface is to create a simple burst mode, read/write interface and transaction protocol that can be used by both memories and peripherals.  The IOs are derived from LPDDR1 for the 1.8-V HyperBus Interface and from legacy NOR for the 3.0-V HyperBus Interface.  Nothing exotic has been deployed, just an optimal usage of existing, market-tested signaling technology.

HyperFlash™ product portfolio

Spansion’s current NOR flash family of HyperFlash memories includes 128-Mb, 256-Mb and 512-Mb products.  These initial offerings are compatible with either 1.8-V or 3.0-V operating voltages.  Engineering samples of the 512-Mb device are available today with fully qualified parts available in the third quarter of 2014.  The 128-Mb and 256-Mb HyperFlash densities will follow in early 2015.  Spansion will develop higher or lower densities depending upon market demand.

 

Emerging high-performance applications demand increasingly fast read throughputs from NOR-flash memory devices.  At the same time, demand for cost-savings and efficiency is driving intense scrutiny of the number of pins required to implement a memory subsystem.  The Spansion HyperBus Interface was developed to satisfy the need for higher read/write performance while remaining sensitive to the pin-count constraints of modern microcontrollers.  The Spansion HyperBus Interface has the ability to satisfy the memory requirements for both volatile and non-volatile memories in a large swath of high-performance applications.  Although Spansion’s focus is to place memory on the HyperBus Interface, the bus protocol is intended to be general purpose, leaving open the possibility for the introduction of non-memory peripheral devices.

 

Related: article on EDN; Spansion
HyperFlash web site

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