Improve system quality through joint qualification

A proactive approach between the customer and silicon supplier optimizes system performance by testing known issues and catching unknown ones.

Takeaways

  • Joint qualification uncovers design flaws
  • Test sample prep speeds future failure analysis
  • Usage testing demonstrates product  quality

Maybe some of you have already been in this situation: You are offering to implement a new technology for your customers because you are convinced it offers them many advantages or solves a current problem.   For example, the need for more data throughput or faster boot time in automotive systems. Automotive customers especially will always ask first, “Do you have experience with this technology? How is it behaving in the field? How many parts are already shipped?” And you would have to tell them, “You would be the first one to use it.”

 

With high quality and zero failure being critical in the automotive industry, it is understandable that automotive customers are conservative in implementing new technologies. In our experience, however, joint qualification (JQ) can be a way to persuade them to overcome their fear of risk, use the newest technology, and benefit from the advantages.

 

Worth the time and effort

Joint qualification is a proactive approach to increase quality. In JQ, the customer assembles a sample part in a real customer platform, which then undergoes testing by both customer and silicon supplier. The goal is to demonstrate not only a qualified memory but also a complete qualified system.

 

The outcome of JQ is the possibility to improve quality and reliability proactively because we test known issues in a customer system in order to check if these issues are eliminated. JQ also allows us to potentially catch unknown issues by testing the interaction between the application usage and the hardware components, something that is not covered in a production test. JQ can prevent failures at an early stage and over system lifetime. In addition, it gives the possibility to optimize system performance by increasing data throughput between memory and the chipset.

 

It is no secret that JQ requires time, effort and resources. In our opinion, it is a worthwhile approach. If a potential issue with a system or device is discovered during JQ, the investigation has already paid off because you now have the opportunity to improve the quality for field usage. Perhaps an even more important consideration is how it can help in the unfortunate event that a device fails upon deployment.

 

Be prepared for failures

Imagine you get a field return from a customer, who will expect you to find the issue and solve the problem very quickly. In this case, it helps to be prepared and to be able to connect high-end analysis tools to your platform. Current high-end PCBs such as automotive cluster or infotainment systems that use BGA packages are not designed for deep system investigations. As a result, it is extremely difficult to connect logic analyzers, oscilloscopes, or other instruments close to the flash to capture exactly what happened on the flash bus at the time the failure occurred. By the way, this procedure also applies for system issues, but in order to find this out, we must be able to connect these high-end tools. The problem is that preparing a multilayer PCB for a deep analysis of devices in a BGA package may take weeks. This is seldom acceptable for a customer.

 

A first or additional step to a complete JQ may involve preparing a new customer platform that allows a detailed and deep failure analysis to be performed immediately if necessary. The silicon supplier also can perform some of the qualification work in parallel to the qualification done by the customer. This will help reduce time to market, which offers an additional value. Finally, when it comes to system performance and collaboration between customers and vendors, the JQ process allows us to learn from each other.

 

JQs in practice

The usual procedure for a joint qualification with the customer takes place on their system. This qualification work can be done both on the customer and vendor side. As a silicon supplier, Spansion starts its testing on a customer-supplied system after adding debug capabilities to it. Next, we characterize the Spansion devices before and after exercising them using our automated test equipment (ATE) to detect any impact of customer application usage or production stresses. Finally, the testing team gives the feedback to our Spansion engineering groups so that we release the best possible product in the future.

 

While checking and testing Spansion devices in the customer system, it is key to be as close as possible to a customer-relevant system and application usage. We review the real customer system versus our own worst-case parameters and also test the real customer production methods versus the impact on the behavior of our own device. After that, we can recommend best practices to maximize robustness and determine the best settings to optimize system performance. Additionally, we are able to identify gaps and/or miscorrelations in customer methods versus our own test methods at Spansion.

 

To minimize failure rate, use automotive-grade parts produced and tested to production part approval process (PPAP) standards. This guarantees failure rates on the order of very low ppm. In order to further improve the quality of a customer system, it must be tested for all critical known issues from previous technologies. This approach creates a test protocol that most closely simulates the customer application. It should detect potential known issues that may not be caught in a product test because of differences in the environment for production testing versus that of the customer platform. In addition, new features need to be tested in a customer platform to determine whether the system environment or customer usage model is susceptible to the new technology and features.

 

It definitely pays off to intensively test the customer usage profile in the customer system to find existing and, in particular, potential new issues introduced by the interaction between the system behavior and the flash technology. During our JQs with our customers, we at Spansion strive to best leverage all advantages of the newest flash memory, such as the fast page read on the 65-nm flash technology and new technologies like error code correction (ECC) that can eliminate potential bit flips.

 

Experiences and examples

As I noted above, it is crucial to plan for system optimization or failure analysis by preparing the customer platform to connect to a logic analyzer. This is not a standard step, but it enables the customer and us to react at once in case any problems or failures in the system arise. The Spansion Wing Board is a small board similar in size to the flash BGA package that is soldered between the PCB and the flash memory module (see figure 1). This board makes it possible to connect the device to a logic analyzer using matched impedance connectors (MICTORs). In the best case, a BGA socket and not the flash itself should be soldered on top of the Wing Board, which allows the user to immediately plug a memory device into the socket and start the investigation. In addition, a crosscheck can be done to see if the failure persists when the flash memory is installed on different hardware.

 

quality pic 1

Figure 1: The Wing Board can be soldered to the PCB and topped by a BGA socket to make it easy to test memory components.

As an example, consider a test process for an automotive application. The Wing Board allowed us to quickly install flash memory and evaluate the application software porting to the customer platform and its OS. Using our flash file system (FFS) and test software, we conducted a stress test between the hardware and software and characterized the device in the customer’s application. Next, we checked for previously identified error sources. We tested the MCU flash timing and used critical FFS functions (erase suspend, power fail safe, garbage collection, etc.) in order to catch potential issues based on the device hardware and software interaction. This allowed us to efficiently cover all known potential errors identified for a well-characterized flash technology and draw conclusions.

 

After this, we checked for new device features such as ECC and tested the application usage in terms of both hardware and customer-specific software. We also tested the system for the effects of stress caused by fabrication steps such as inspection and reflow. Here, we used the methods of preconditioning, pre-characterization, and customer exposure, closing with post-characterization.

 

Using this process, we were able to not only qualify the flash and the system but also investigate and enhance read data throughput, improve boot time, and optimize other performance features.

 

The JQ process delivers a number of benefits to OEMs, including improved time-to-market and the ability to quickly ramp up with the latest flash technology. With a well-developed process and tools like the Wing Board, developers can easily check all key parameters to ensure highest quality performance and to catch any potential issues early in the process. This method also provides a powerful tool for process improvement, allowing designers to reduce system boot time based on the latest technologies and features. All in all, JQ enables best-in-class quality for a customer system and makes it easy for OEMs to develop new platforms based on the latest technology.

 

10 steps to successful joint qualification

  • Focus on the known critical parameters first and then add more per customer’s choice.
  • Review timing setup (boot, asynchronous read, page read, burst read).
  • Review typical device usage (program/erase history, sector usage mapping, flash file system, and SW usage).
  • Test Vcc to +100 mV over spec. Check noise and also confirm that Vcc is stable in the system.
  • Test temperature to +5° over spec.
  • Review design and loading.
  • Check for bit-flip robustness and ECC.
  • Evaluate impact of customer production or application usage profiles to bit integrity.
  • Cycle through program/erase steps.
  • Test for mechanical stresses from fabrication.
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